Motifs of Ring Oscillators

Motifs of Ring Oscillators #

This lecture is focused on placement constraints using ring oscillators as an example. Four different ring oscillators (different in their placement) will be implemented with all the accompanying constraint difficulties. ,

Table of Contents #

Starting Template #

Clone the starting template from gitlab:

A Few Notes #

Synthesis Hierarchy #

One setting that has a large impact upon how Vivado synthesizes a design is flatten_hierarchy. Vivado has three options for synthesis `flatten_hierarchy:

  1. Full - Vivado flattens all modules into one module, then synthesizes that. This is generally the most resource efficient, but it can be hard to troubleshoot bugs in the design.
  2. None - Vivado keeps all hierarchy. This makes the design easier to debug, but less resource efficient.
  3. Rebuilt - This is the default setting. Vivado flattens the design, synthesizes, then tries to rebuild the hierarchy after synthesis. The goal is to create a happy medium between debug-ability and efficiency.

Since these lectures are for education, we will generally set flatten_hierarchy to None.

Basic Ring Oscillator #

First Go #

Create the file src/verilog/ring_osc_1.v and add the following contents:

// Time scale is used for simulation
`timescale 1ns / 1ps

module ring_osc_1 #(
        // Parameters
        // Must be odd...could add logic to
        // remove odd requirement.
        parameter integer N = 101
    ) (
        // Define the inputs and outputs to the module
        output  wire        ro_out
    );

    // Create the wires
    wire [N-1:0] ro;

    // The Ring Oscillator
    assign ro = {~ro[N-2:0],~ro[N-1]};

    // Assign output
    assign ro_out = ro[0];

endmodule

Create the file src/verilog/top.v and add the following contents:

// Time scale is used for simulation
`timescale 1ns / 1ps


module top(
    // Define the inputs and outputs to the module
    output wire    [3:0]   ja
    );

    // Instantiate Ring Oscillator
    ring_osc_1 #(.N(201)) ro1_inst0 (
        .ro_out(ja[0])
    );

endmodule

Create the file src/constraints/arty_constraints.xdc and add the following contents

#########################################
## Hardware Constraints
#########################################

### Pmod Header JA
set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports {ja[0]}]
set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {ja[1]}]
set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {ja[2]}]
set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS33} [get_ports {ja[3]}]

Synthesize the design and open the schematic. WAIT! It’s empty! Why?

Synthesis and Implementation Directives #

Synthesis and implementation directives are not apart of the verilog standard. Instead, they are extra information to help Vivado know how to synthesize and implement the verilog properly. Vivado also calls synthesis and implementation directives, “Vivado Design Suite Properties”. See the documentation for the full list of properties available.

In our case we need to prevent the optimizer in Vivado from removing our ring oscillator LUTs that to the optimizer have no purpose. There are two different properties/directives that do similar operations, but have important implications.

  • keep - Prevent optimization in synthesis. Any objects (except modules) with the dont_touch parameter attached to it are not optimized.
  • dont_touch - This is the same as keep, except it is forward annotated which means that synthesis does not remove the property. Thus, implementation will also keep the elements with the property attached.
  • keep_hierarchy - Prevents optimization in hierarchy (i.e., modules). This prevents the optimizer from crossing a hierarchy boundary.

So in our case, we want to use the dont_touch parameter. The updated ring oscillator code becomes:

// Time scale is used for simulation
`timescale 1ns / 1ps

module ring_osc_1 #(
        // Parameters
        // Must be odd...could add logic to
        // remove odd requirement.
        parameter integer N = 101
    ) (
        // Define the inputs and outputs to the module
        output  wire        ro_out
    );

    // Synthesis and implementation directive!
    // Create the wires
    (* dont_touch = "yes" *) wire [N-1:0] ro;

    // The Ring Oscillator
    assign ro = {~ro[N-2:0],~ro[N-1]};

    // Assign output
    assign ro_out = ro[0];

endmodule

Now our ring oscillator works!

P-Blocks #

Placement Blocks (P-Blocks) are a quick and dirty way to provide a high level placement constraint upon the design.

Adding Second Ring Oscillator #

Let’s add another instantiation of the ring oscillator to top.v for the P-Block example. The updated top.v should look like the following:

// Time scale is used for simulation
`timescale 1ns / 1ps


module top(
    // Define the inputs and outputs to the module
    output wire    [3:0]   ja
    );

    // Instantiate Ring Oscillator 0
    ring_osc_1 #(.N(201)) ro1_inst0 (
        .ro_out(ja[0])
    );

    // Instantiate Ring Oscillator 1
    // Constrain with P-Blocks
    ring_osc_1 #(.N(201)) ro1_inst1 (
        .ro_out(ja[1])
    );

endmodule

Run Synthesis and open the synthesized design. This produces an unexpected result! One of the ring oscillators is removed! This is because the optimizer saw the two instantiations were equivalent and removed one.

We can prevent this by added another directive to prevent the optimizer from crossing a hierarchy boundary. At the moment, we only need to apply the directive to one oscillator, but for future parts of the example, we will apply it to both:

// Time scale is used for simulation
`timescale 1ns / 1ps

module top(
    // Define the inputs and outputs to the module
    output wire    [3:0]   ja
    );

    // Instantiate Ring Oscillator 0
    (* KEEP_HIERARCHY = "TRUE" *) ring_osc_1 #(.N(201)) ro1_inst0 (
        .ro_out(ja[0])
    );

    // Instantiate Ring Oscillator 1
    // Constrain with P-Blocks
    (* KEEP_HIERARCHY = "TRUE" *) ring_osc_1 #(.N(201)) ro1_inst1 (
        .ro_out(ja[1])
    );

endmodule

After Synthesizing and opening the synthesized design, we get two oscillators as intended.

Applying P-Block #

In the synthesized design, open the Device tab. Then in the Netlist tab, right click on ro1_inst1 and select Floorplanning > Draw P-Block.

Click and drag a purple box over the top left slice, then let go. A window will pop up askign to confirm creating the P-Block. Click Ok.

Then a statistics tab will pop up, showing the utilized resources in the P-Block.

Then save the synthesis configuration with Ctrl-s. A window will pop up asking to confirm saving the new synthesis config, click Ok.

Then confirm saving the new constraints to the existing constraints file.

This will automatically add the following to arty_constraints.xdc (you don’t need to do anything!).

create_pblock pblock_ro1_inst1
add_cells_to_pblock [get_pblocks pblock_ro1_inst1] [get_cells -quiet [list ro1_inst1]]
resize_pblock [get_pblocks pblock_ro1_inst1] -add {SLICE_X0Y175:SLICE_X7Y199}

Running Implementation shows the luts loosely placed in the boundary. This is a key point: P-Blocks are not strict. They are guidelines to the floorplanner.

Combinatorial Loop Error #

Let’s take a quick aside to address the critical warnings. At this point, Vivado is unhappy we have a loop of combinatorial elements; usually, this is a bug in a digital logic design. So we want to explicitly tell Vivado this is intended. We do this by attaching the ALLOW_COMBINATORIAL_LOOPS parameter to the offending nets. We only want to attach the parameter to the offending nets so to do that, we will limit the scope of our command. The command current_instance INSTANCE sets the scope to INSTANCE where INSTANCE is a module instance; that means Vivado only knows what is in that instance and everything below. If we execute current_instance without an argument, it will reset the to the highest level of hierarchy. Add the following to the top of arty_constraints.xdc.

#########################################
## ALLOW_COMBINATORIAL_LOOPS
#########################################
## Here you should only set the property as locally as possible 
## since this is a good check if your design is broken.

current_instance ro1_inst0
set_property ALLOW_COMBINATORIAL_LOOPS true [get_nets -hierarchical]
current_instance -quiet; ## Reset the scope

current_instance ro1_inst1;
set_property ALLOW_COMBINATORIAL_LOOPS true [get_nets -hierarchical];
current_instance -quiet; ## Reset the scope

## snip...

Please note the semi-colon between the end of the line and the inline comment! TCL doesn’t support inline comments so you have to explicitly set a command delineation with ;.

Running synthesis and implementation will now execute without critical errors. Note, this does not explicitly prevent Vivado from running timing analysis on the loop (which it shouldn’t). We will address that later.

Using FPGA Primitives #

Ideally, we want as much control as possible in the placement of our ring oscillator. In order to do that, we need to implement the ring oscillator in LUTs.

Instantiating Primitives #

Primitives are the physical building blocks of an FPGA design. The primitives available are dependent upon the specific FPGA (or series of FPGAs), but there are some primitives common to all FPGAs. Generally, FPGAs don’t have AND, OR, NOT, etc., gates; instead, all combinatoric logic is implemented using Look Up Table primitives (LUTs). Usually, all flip-flops (SR, JK, etc.) are implemented with D-Flip-Flops that have various types of sets/resets. The primitives available in Xilinx Series 7 FPGAs can be found here: Series 7 Design Elements.

To build our ring oscillator, we will use LUT1 (i.e., 1 bit LUTs). The truth table is implemented with an INIT parameter which is a bit mask where the row of the table corresponds to the bit location and the bit value corresponds to the output of value for the row. For example, consider the LUT4:

//  Truth Table to determine INIT value for a LUT3
//      ______________
//     | I2 I1 I0 | O |
//     |--------------|
//     |  0  0  0 | 0 |\
//     |  0  0  1 | 1 | \ = 4'b1110 = 4'hE --------------+
//     |  0  1  0 | 1 | /                                |
//     |  0  1  1 | 1 |/                                 |
//     |----------|---|                       INIT = 8'h1E
//     |  1  0  0 | 1 |\                                |
//     |  1  0  1 | 0 | \ = 4'b0001 = 4'h1 -------------+
//     |  1  1  0 | 0 | /
//     |  1  1  1 | 0 |/
//     ----------------

The INIT parameter is 8'h1E. Then the LUT4 can be instantiated with:

   LUT4 #(
      .INIT(8'h1E)  // Specify LUT Contents
   ) LUT4_inst (
      .O(out),   // LUT general output
      .I0(in0), // LUT input
      .I1(in1), // LUT input
      .I2(in2), // LUT input
      .I3(in3)  // LUT input
   );

With that in mind, create the file src/verilog/ring_osc_2.v and add it to the project with the following contents:

// Time scale is used for simulation
`timescale 1ns / 1ps

module ring_osc_2 #(
        // Parameters
    ) (
        // Define the inputs and outputs to the module
        output  wire        ro_out
    );

    // Create the wires
    (* dont_touch = "yes" *) wire [1:0] ro;

    //  Truth Table to determine INIT value for an inverter LUT1
    //      ________
    //     | I0 | O |
    //     |--------|
    //     |  0 | 1 |--------|
    //     |  1 | 0 |-------||
    //     ----------  = 2'b01
    LUT1 #(
      .INIT(2'b01)  // Specify LUT Contents
    ) LUT1_inst0 (
      .O(ro[1]),   // LUT general output
      .I0(ro[0])  // LUT input
    );

    assign ro[1] = ro_out;

endmodule

Notice the LUT is equivalent to an inverter.

Instantiate the new module in top.v.

// snip..
    // Instantiate Ring Oscillator 2
    // LUT1s
    (* KEEP_HIERARCHY = "TRUE" *) ring_osc_2  ro2_inst0 (
        .ro_out(ja[2])
    );
// snip...

Synthesize the design. The truth table for the LUT can be found by selecting the LUT out of the netlist.

Constraining Primitives #

Now we can constrain our LUTs to specific locations. There are two levels to the physical placement: LOC and BEL. LOC is the slice, ram block, dsp block, etc. and BEL is the component within the block to use. Per the documentation, the BEL parameter MUST be set before the LOC parameter, otherwise an error will be throw.

To constrain our LUT1, add the following to the arty_constraints.xdc,

## snip...

#########################################
## Detailed Placement Constraints
#########################################
set_property BEL A6LUT [get_cells ro2_inst0/LUT1_inst0]
set_property LOC SLICE_X1Y1 [get_cells ro2_inst0/LUT1_inst0]

## snip...

This selects the A6LUT in the SLICE_X1Y1 block.

Run Synthesis and Implementation. Opening the implementation and selecting the LUT shows the placement exactly as we constrained.

Ring Oscillator #

Now, we can use the LUTs to build a ring oscillator.

Verilog Generate Functions #

Typing out the hundreds of thousands of LUTs needed to make a ring oscillator is not feasible. Instead, Verilog has the wonderful generator operator to help out.

In src/verilog/ring_osc2.v remove the testing LUT definition and add the generator code to produce the following:

// Time scale is used for simulation
`timescale 1ns / 1ps

module ring_osc_2 #(
        // Parameters
        parameter integer N = 101
    ) (
        // Define the inputs and outputs to the module
        output  wire        ro_out
    );

    // Create the wires
    (* dont_touch = "yes" *) wire [N-1:0] ro;

    // Special type just for generators
    genvar i;

    // Create an inverter delay line
    generate
        for (i = 0; i <= N-2; i = i + 1)
        begin: gen_ro2
            LUT1 #(
              .INIT(2'b01)  // Specify LUT Contents
            ) lut1_inst (
              .O(ro[i+1]),   // LUT general output
              .I0(ro[i])  // LUT input
            );
        end
    endgenerate

    // Complete the loop
    LUT1 #
(
      .INIT(2'b01)  // Specify LUT Contents
    ) loop_lut1_inst (
      .O(ro[0]),   // LUT general output
      .I0(ro[N-1])  // LUT input
    );

    assign ro[N-1] = ro_out;

endmodule

Now we can run synthesis and implementation.

Constraining the Ring Oscillator #

Of course, we need to add the ALLOW_COMBINATORIAL_LOOPS parameter to all the nets in the new ring oscillator.


## snip...
current_instance ro2_inst0;
set_property ALLOW_COMBINATORIAL_LOOPS true [get_nets -hierarchical];
current_instance -quiet; ## Reset the scope
## snip...

And also remove the constraints for the single LUT.

Until now, we have been using *.xdc files for constraints. XDC files use a reduced TCL language: they don’t support loops or control logic, but they do support better constraint error handling. To handle the more complicated constraints that require loops and control logic, normal TCL files can be added as constraints.

Create and add src/constraints/ro2_inst0_placement_constraints.tcl to the project. Since it is a placement constraint, it is ONLY valid during implementation; so deselect Synthesis and Simulation as shown below.

First Attempt #

In order to constrain the LUTs we first need to know what they are called. Synthesizing the design and looking at the generated leaf cells shows they are named as, gen_ro2[i].lut2_inst where i is the genvar index.

With the name in mind, we can write a TCL loop to constrain the cells as shown below.

puts "\nEvaluating ro2_placement_constraints...\n"

## Same number of gates as in the ring oscillator 
set N 101

## Constrain the generated LUTs
for {set i 0} {$i <= [expr { $N - 2 }]} {incr i} {
    puts "Constraining ro2_inst0/gen_ro2\[$i\].lut1_inst to A6LUT on SLICE_X1Y$i"
    set_property LOC "SLICE_X1Y$i" [get_cells "ro2_inst0/gen_ro2\[$i\].lut1_inst"]
}

## Constrain the loop LUT
puts "Constraining ro2_inst0/loop_lut1_inst to A6LUT on SLICE_X0Y0"
set_property LOC "SLICE_X0Y0" [get_cells "ro2_inst0/loop_lut1_inst"]

puts "\nDone evaluating ro2_placement_constraints...\n"

Running implementation now shows the LUTs are constrained in one line (see below).

However, this is not ideal, because we are only using one BEL site within a Slice.

Second Attempt #

For a second attempt let’s add another instantiation of the ring oscillator for comparision. Now, the whole top.v looks like

// Time scale is used for simulation
`timescale 1ns / 1ps

module top(
    // Define the inputs and outputs to the module
    output wire    [3:0]   ja
    );

    // Instantiate Ring Oscillator 0
    (* KEEP_HIERARCHY = "TRUE" *) ring_osc_1 #(.N(201)) ro1_inst0 (
        .ro_out(ja[0])
    );

    // Instantiate Ring Oscillator 1
    // Constrain with P-Blocks
    (* KEEP_HIERARCHY = "TRUE" *) ring_osc_1 #(.N(201)) ro1_inst1 (
        .ro_out(ja[1])
    );

    // Instantiate Ring Oscillator 2
    // LUT1s
    (* KEEP_HIERARCHY = "TRUE" *) ring_osc_2  ro2_inst0 (
        .ro_out(ja[2])
    );

    // Instantiate Ring Oscillator 2
    // LUT1s with better constraint
    (* KEEP_HIERARCHY = "TRUE" *) ring_osc_2  ro2_inst1 (
        .ro_out(ja[3])
    );

endmodule

And of course, add the ALLOW_COMBINATORIAL_LOOPS parameter. The complete arty_constraints.xdc should look like

## Constraints

#########################################
## ALLOW_COMBINATORIAL_LOOPS
#########################################
## Here you should only set the property as locally as possible 
## since this is a good check if your design is broken.

current_instance ro1_inst0
set_property ALLOW_COMBINATORIAL_LOOPS true [get_nets -hierarchical]
current_instance -quiet; ## Reset the scope

current_instance ro1_inst1;
set_property ALLOW_COMBINATORIAL_LOOPS true [get_nets -hierarchical];
current_instance -quiet; ## Reset the scope

current_instance ro2_inst0;
set_property ALLOW_COMBINATORIAL_LOOPS true [get_nets -hierarchical];
current_instance -quiet; ## Reset the scope

current_instance ro2_inst1;
set_property ALLOW_COMBINATORIAL_LOOPS true [get_nets -hierarchical];
current_instance -quiet; ## Reset the scope



#########################################
## Hardware Constraints
#########################################

### Pmod Header JA
set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports {ja[0]}]
set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {ja[1]}]
set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {ja[2]}]
set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS33} [get_ports {ja[3]}]

#########################################
## P-Block Constraints
#########################################

create_pblock pblock_ro1_inst1
add_cells_to_pblock [get_pblocks pblock_ro1_inst1] [get_cells -quiet [list ro1_inst1]]
resize_pblock [get_pblocks pblock_ro1_inst1] -add {SLICE_X0Y175:SLICE_X7Y199}

Now create the file src/constraints/ro_inst1_placement_constraints.tcl and add the following contents:

puts "\nEvaluating ro2_inst1_placement_constraints...\n"

## Same number of gates as in the ring oscillator 
set N 101

## Constrain the generated LUTs
for {set i 0} {$i <= [expr { $N - 2 }]} {incr i} {
    set m [expr {$i % 4}]
    set k [expr {$i / 4}]
    if {$m == 0} {
        puts "Constraining ro2_inst1/gen_ro2\[$i\].lut1_inst to A6LUT on SLICE_X3Y$k"
        set_property BEL "A6LUT" [get_cells "ro2_inst1/gen_ro2\[$i\].lut1_inst"]
        set_property LOC "SLICE_X3Y$k" [get_cells "ro2_inst1/gen_ro2\[$i\].lut1_inst"]
    } elseif {$m == 1} {
        puts "Constraining ro2_inst1/gen_ro2\[$i\].lut1_inst to B6LUT on SLICE_X3Y$k"
        set_property BEL "B6LUT" [get_cells "ro2_inst1/gen_ro2\[$i\].lut1_inst"]
        set_property LOC "SLICE_X3Y$k" [get_cells "ro2_inst1/gen_ro2\[$i\].lut1_inst"]
    } elseif {$m == 2} {
        puts "Constraining ro2_inst1/gen_ro2\[$i\].lut1_inst to C6LUT on SLICE_X3Y$k"
        set_property BEL "C6LUT" [get_cells "ro2_inst1/gen_ro2\[$i\].lut1_inst"]
        set_property LOC "SLICE_X3Y$k" [get_cells "ro2_inst1/gen_ro2\[$i\].lut1_inst"]
    } else {
        puts "Constraining ro2_inst1/gen_ro2\[$i\].lut1_inst to D6LUT on SLICE_X3Y$k"
        set_property BEL "D6LUT" [get_cells "ro2_inst1/gen_ro2\[$i\].lut1_inst"]
        set_property LOC "SLICE_X3Y$k" [get_cells "ro2_inst1/gen_ro2\[$i\].lut1_inst"]
    }
}

## Constrain the loop LUT
puts "Constraining ro2_inst1/loop_lut1_inst to A6LUT on SLICE_X0Y0"
set_property BEL "A6LUT" [get_cells "ro2_inst1/loop_lut1_inst"]
set_property LOC "SLICE_X2Y0" [get_cells "ro2_inst1/loop_lut1_inst"]

puts "\nDone evaluating ro2_inst1_placement_constraints...\n"

This is a far more efficient placement.

It is a simple matter from here to create 2D grids of LUTs or any other design.

Timing Exceptions #

Now let’s address the High Severity timing exceptions. Opening the Timing information in the implemented design shows high severity loops.

The warnings are because Vivado doesn’t know how to handle static timing analysis (STA) on combinatorial loops and in reality STA is meaningless for loops. For our ring oscillator design we don’t want any timing analysis to be executed on the ring oscillators so let’s disable it.

Add the following four lines to arty_constraints.xdc

set_disable_timing [get_cells ro1_inst0/*]
set_disable_timing [get_cells ro1_inst1/*]
set_disable_timing [get_cells ro2_inst0/*]
set_disable_timing [get_cells ro2_inst1/*]

Now implementation will not have any timing errors.