Introduction to Verilog and FPGA Design

Introduction to Verilog and FPGA Design #

The following is a brief introduction to Verilog and FPGA design for Xilinx FPGAs. This is a work in progress and there are probably many mistakes.

What is Verilog and What it is not #

  • Verilog is NOT a programming language
    • At a high level programming languages take human readable code and turn them into instructions a processor can understand
  • Verilog is a Hardware Descriptor Language (HDL).
    • HDL’s are human readable descriptions of logic circuits.
    • HDL circuit descriptions may be synthesized and implemented on FPGAs or ASICs.
    • Note: the term “HDL” can mean a general hardware descriptor language or a specific hardware descriptor language called, “HDL”. Only context differentiates.

High Level Process # 

flowchart TB

verilog([Verilog])
constraints([Constraints])
mconstraints([Hardware Constraints])

synthesis[Synthesis]
implementation[Implementation]
bitgen[Bitstream Generation]
fpga[FPGA]

verilog --> synthesis
constraints --> synthesis
mconstraints --> implementation
synthesis --> implementation
implementation --> bitgen
bitgen --> |Bitstream|fpga

The Four Things You Can Do Verilog #

  1. Instantiation of variables: wires, regs
  2. Combinational logic: assign
  3. Sequential logic: always
  4. Instantiation of modules

Constraints #

  • Tell synthesis/implementation how to build your design
  • Written in TCL
  • This includes
    • Routing (i.e., clock signals vs. data signals)
    • Timing
    • Placement
    • Chip Pads
    • And lots more…

Resources #

Speed Run #

The goal is to run through a basic “hello world” and get a high level perspective of each step involved.

Creating The Project #

Open Vivado and select “Create Project”

\ | 500

Set the name and location of the project. Select “Create project subdirectory”. \ | 500

Set the project type to “RTL Project” and don’t specify the sources at this time. \ | 500

Here you set the FPGA and there are two ways to do it.

Option 1: Specify the FPGA #

Select the FPGA that is on the development board.

If you have an Arty A7-100T use: XC7A100TCSG324-1* If you have an Arty A7-35T use: XC7A35TICSG324-1L

This is specified in the documentation for the dev boards.

\ | 500

Option 2: Use a provided Board File #

First you must have the board files from Digilent installed. Installation proceedures can be found here.

Once those are installed, then you can select the “Arty A7-T100” board.

\ | 500

After clicking finish you should land on the home page. \ | 500

Adding Design Source Verilog #

Now we can add some Verilog to the project.

Under “Sources” click on the big “+” sign. \ | 500

Select “Add or create design sources”. \ | 500

Select “Create File”. \ | 500

Name the file “top.v”. \ | 500

Now you should see the file in the list; click “finish.” \ | 500

Click “Ok”. We will delete all the default contents of the file so it doesn’t matter. \ | 500

Editing the Verilog #

Now there is a design source called, “top.v”.

\ | 500

Open the file, delete all the default contents and past the following:

// Time scale is used for simulation
`timescale 1ns / 1ps

// All verilog code must be wrapped in modules.
// There will be one "top" module that is the highest module.
// Vivado automatically sets any module named "top" as the top.
module top(
    // Define the inputs and outputs to the module
    output  wire        led,
    input   wire        CLK100MHZ
    );
   
    // Counter for clock divider
    reg     [24:0]  counter = 24'd0;

    // Clock divider
    // Count up on every 100MHz positive clock edge
    // The register will overlfow and loop
    always @(posedge CLK100MHZ)
    begin
        counter <= counter + 1;
    end

    // Assign the last bit in the counter to the LED. 
    // Thus the LED will blink every 100e6/2^25 Hz
    assign led = counter[24];

endmodule

Don’t forget to save!!

Adding Constraints #

Constraints tell Vivado how the logic should be implemented on the physical FPGA. This includes things like physical pads, timing, routing, placement, etc.

A default constraints file for the arty dev boards that includes all of the wired pads can be found here, but we will use our own.

Click the big plus sign under Sources again. \ | 500

Select, “Add or create constraints.” \ | 500

Select “Create File” and name the file, “arty_constraints.xdc.” \ | 500

Click “Ok” and then click “Finish”.

Open the newly created file, delete the default contents and copy the following into it:

## Constraints file for the speed run

#####################
### Clock 
#####################
## Create the clock port which is wired to a 100MHz crystal oscillator on the dev board
set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; ##IO_L12P_T1_MRCC_35 Sch=gclk[100]
## This tells vivado to route the signal as a clock
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];


#####################
### LED
#####################
## Set the port to the package pin wired to the LED on the dev board
set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { led }]; ##IO_L24N_T3_35 Sch=led[4]

Yay! Now you have some constraints.

Adding Simulation Sources #

Let’s run some simulations to make sure that the Verilog does what we want it to.

Click the big plus sign under Sources and select, “Add or create simulation sources”. \ | 500

Click “Create File” and name the file “top_sim.v”. \ | 500

Click finish. | 500

Don’t change anything here; we will copy our own stuff in. Click Ok.

\ | 500

Open the file, delete the default contents and copy the following in.

// This time scale sets the time resolution of the ## symbol
`timescale 1ns / 1ps

module top_sim(
    // No io
    );

    // Create dummy wires and registers
    wire        led;
    reg         clk = 0;

    // instantiate the top module
    top top0 (
        .led(led),
        .CLK100MHZ(clk)
    );

    // Create a dummy clock signal 
    // the "##" operator waits the given number of time scales
    // as the time scale is set above. 
    // In this case, it waits 5ns
    always ##5 clk = ~clk;

endmodule

Running Simulations #

Select “Run Simulation” then choose, “Run Behavioral Simulation.”

The simulation doesn’t run for long enough to see the LED flip, so set the time extension to 300ms and press the arrow with the (T) under it to set the simulation to run for another 300ms.

Once it finishes (and you zoom out), you should seed the LED flip on.

Synthesis/Implementation/Bitstream Generation #

Now we can synthesize, implement and generate the bitstream.

You could press each button (Run Synthesis, Run Implementation and Generate Bitstream) in order, or just press Generate Bitstream and it will run the other two first.

Booting onto the FPGA #

Now we are ready to boot the the FPGA.

First plug in the FPGA. Then open the Hardware Manager.

Click “Open Target” and “Autoconect”.

Once the target is connected, select “Program device”

Click “Program”.

Give it a minute and then the LED should blink. Yay!

Language Basics #

Comments #

Line comments

\\

Block Comments

\*

*\

Constants #

Since Verilog is the human readable representation of physical hardware, constants always have an associated “size” that is the number of registers required to hold the constant. The notation for a constant is

<size>'<base><number>

where size is the number of bits, base is the radix of the number and number is the value. There are four valid bases/radixes.

  • b - binary
  • o - octal
  • d - decimal
  • h - hex

Some examples:

## 1 bit with value 0
1'b0

## 1 bit with value 0
1'd0

## 16 bit with value 32768
16'h8000

If the size is not specified (don’t do this!), then it defaults to the default size of the synthesizer (I think 32 bits for Vivado?).

Strings #

If a string is used, it is converted to the equivalent ACII characters.

"hello world"

Wires and Registers #

There are two connecting entities in Verilog: wires and registers.

Wires #

A wire is just like a physical peice of wire; it connects two circuit elements together. Wires may be “bussed” together to make notation easier.

// Single wire instantiation
wire mywire; 

// Bus instantiation
wire [5:0] mybuswire;

Registers #

Registers are exactly like a computer register; they store a one bit value. Registers may be “bussed” together to store multiple bits. Since registers store values, it is good practice to always give a default initialization value.

// single register instantiation
reg myreg = 0;

// bussed register instantiation
reg [7:0] mybussedreg = 0;

Integers #

Integers are a register with a default size of 32 bits.

integer myint = 45;

Modules #

Module Declaration #

All logic must be wrapped in a module. Modules have “ports” which are the inputs and outputs to the port.

Verilog Keyword Port Type
input Input Port
output Output Port
inout Bidirectional Port

There are two methods for declaring a module:

Method 1. # 
methodOneModule(a, b, c);
	// Declare the direction of the ports
	input a;
	input b; 
	output c;
	
	// Declare the type of the ports
	wire a;
	wire [3:0] b;
	reg c;
	
	// Module logic.
endmodule

Note, you could also declare the type with the direction of each port in one line.

methodOneModule(a, b, c);
	// Declare the direction and type of the ports
	input wire a;
	input wire [3:0] b; 
	output reg c;
	
	// Module logic.
endmodule
Method 2. #

This is technically the ANSI C style.

methodTwoModule(
	input wire a,
	input wire [3:0] b,
	output reg c // Note no comma!!
);
	// Module logic
endmodule

Module Instantiation #

There are two methods for instantiating modules based upon named or positional port assignment. I HIGHLY recommend only using named port assignment. It removes the possibility of errors tenfold.

Positional Port Assignment # 
module top();
	wire A;
	wire [3:0] B;
	reg C;
	
	methodTwoModule myModInst (A,B,C);
	
endmodule
Named Port Assignment # 
module top();
	wire A;
	wire [3:0] B;
	reg C;
	
	methodTwoModule myModInst (
		.a(A),
		.b(B),
		.c(C) // Note no comma!
	);
	
endmodule

Module Parameters #

Good HDL (like good code) is modular and reusable. To make modules reusable, parameters are a wonderful tool.

Declaration # 
modWithParam ##(
	parameter N = 2, // Default value given here
	parameter M = 4  // Note no comma!
) (
	input wire a,
	input wire [N:0] b,
	output reg [M:0] c // Note no comma!!
);
	// Module logic
endmodule
Instantiation # 
module top();
	wire A;
	wire [3:0] B;
	reg C;
	
	modWithParam ##(
		.N(8),
		.M(10)
	) myModInst (
		.a(A),
		.b(B),
		.c(C) // Note no comma!
	);
	
endmodule

Combinational Logic #

Logical Operators # 

// Logical Not
assign C = !A;

// Logical And
assign C = A && B;

// Logical Or
assign C = A || B;

Bitwise Operators # 

// Bitwise not
assign C = ~A;

// Bitwise and
assign C = A & B;

// Bitwise or
assign C = A | B;

// Bitwise xor
assign C = A ^ B;

// Bitwise xnor
assign C = A ~^ B;
assign C = A ^~ B;

Shifts # 

// Right shift
assign C = A << 1;

// Left Shift
assign C = A >> 1;

Conditional/Multiplexor # 

// If D is high, C = A, else C = B;
assign C = D ? A : B;

Concatenation and Replication #

Concatenation # 
wire A;
wire B;
wire [1:0] C;

assign C = {A,B};
Replication # 
wire A;
wire [3:0] C;

assign C = { 4{A} };

Sequential Logic #

Sequential logic is built around the always statement.

D flipflop. Assign C to B on the rising edge of A.

always @(posedge A)
begin
	B <= C;
end

Or the negative edge.

always @(negedge A)
begin
	B <= C;
end

Or on the edge of multiple clocks

always @(negedge A1, posedge A2)
begin
	B <= C;
end

Or on the edge of multiple clocks with conditions

always @(negedge A1, posedge A2)
begin
	if (A2 == 1'b1)
	begin
		B <= C;
	end
end

Or multiple conditions

always @(negedge A1, posedge A2)
begin
	if (A2 == 1'b1)
	begin
		B <= C;
	end
	else if (A1 == 1'b0)
	begin
		B <= C;
	end
	else 
	begin
		B <= C;
	end
end

If the statement is only one line, the begin and end pair can be omitted, but be careful!

always @(posedge A)
	B <= C;

and the same with if statements,

always @(negedge A1, posedge A2)
begin
	if (A2 == 1'b1)
		B <= C;
	else if (A1 == 1'b0)
		B <= C;
	else 
		B <= C;
end

Side Note on Blocking vs. Non-blocking Assignment #

There are two different assignment operators within always or initial statements: blocking and nonblocking. The blocking operator means the statments must be executed in order. For example, in the code

initial
begin
	a = b;
	c = d;
end

the asignment of a = b must happen before c = d. Alternatively, non blocking operators are all executed in parallel:

initial
begin
	a <= b;
	c <= d;
end

I.e., the both assignments happen at the same time.

In FPGA design, you really can’t use blocking assignments. The hardware architecture isn’t there. They may be helpful in designing simulations, but outside if that, you will always use the non-blocking assignment.